Dual in-line memory modules (DIMMs) are used in a number of different types of computing systems. DIMMs include multiple dynamic random access memory (DRAM) chips arranged to provide 64 data bits to a data bus within a computing system. The DRAM chips typically provide one (single rank), two (dual rank) or four (quad rank) 64-bit data areas on the DIMM depending on the type and number of DRAM chips used. Optionally, DIMMs include one or more DRAM chips to provide error correction code (ECC) check bits, which are used to verify the integrity of data stored on a DIMM.
Demanding computing systems such as servers and workstations require a high level of performance and reliability. To meet these requirements, these types of computing systems are often equipped with registered DIMMs. Registered DIMMs use a register component to synchronize address and control signals received from a system memory controller and distribute those signals to the DRAM chips on the DIMM. FIG. 1 is a block diagram depicting the main components of one example of a registered DIMM together with representations of some of the signals communicated between the components.
As shown in FIG. 1, registered DIMM 10 includes nine DRAM chips 11, which provide 64 data bits and 8 ECC check bits. Also included in registered DIMM 10 are register component 12 and phase-locked loop (PLL) component 13. Register component 12 receives address and control signals driven by a system memory controller (not shown) to access DRAM chips 11. Register component 12 synchronizes the address and control signals received from the system memory controller and distributes these signals to each of DRAM chips 11. PLL component 13 receives a CLOCK IN signal from the computing system and distributes a CLOCK OUT signal to register component 12 and each of DRAM chips 11. Using a feedback control system, PLL component 13 maintains the CLOCK OUT signal in a fixed-phase relationship with the CLOCK IN signal.
Register component 12 has a feature set that affects the performance and operation of registered DIMM 10. For example, one feature of register component 12 is its output drive strength which is set based on performance requirements and the number of DRAM chips the address and control signals must be driven to by the register component. Other features include command filters and mirroring settings. However, the register feature sets of conventional registered DIMMs are limited and are typically hard wired during assembly. Accordingly, the feature sets of conventional register components generally are not configurable by the end user. This limits the end user's ability to obtain performance improvements from the registered DIMM using existing and potential features of the register component.